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1 ?2015 integrated device technology, inc. february 2015 dsc 3241/13 idt7054s/l features high-speed access ? commercial: 20/25/35ns (max.) ? industrial: 25ns (max.) low-power operation ? idt7054s active: 750mw (typ.) standby: 7.5mw (typ.) ? idt7054l active: 750mw (typ.) standby: 1.5mw (typ.) true fourport memory cells which allow simultaneous access of the same memory locations fully asynchronous operation from each of the four ports: p1, p2, p3, and p4 ttl-compatible; single 5v (10%) power supply available in 128 pin thin quad flatpack package industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information description the idt7054 is a high-speed 4k x 8 fourport? static ram designed to be used in systems where multiple access into a common ram is required. this fourport static ram offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. the idt7054 is also designed to be used in systems where on-chip hardware port arbitration is not needed. this part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when all ports simulta- neously access the same fourport ram location. the idt7054 provides four independent ports with separate control, functional block diagram high-speed 4k x 8 fourport tm static ram memory array column i/o port 1 address decode logic port 2 address decode logic column i/o column i/o port 4 address decode logic port 3 address decode logic column i/o r / w p1 i/o 0p1 -i/o 7p1 ce p1 oe p1 a 0p1 -a 11p1 r/ w p2 ce p2 oe p2 3241 drw 01 i/o 0p2 -i/o 7p2 a 0p2 -a 11p2 r/ w p4 i/o 0p4 -i/o 7p4 ce p4 oe p4 a 0p4 -a 11p4 r/ w p3 ce p3 oe p3 i/o 0p3 -i/o 7p3 a 0p3 -a 11p3
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperature ranges 2 notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. package body is approximately 14mm x 20mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. it is the user?s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. an automatic power down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low power standby power mode. fabricated using cmos high-performance technology, this fourport sram typically operates on only 750mw of power. the idt7054 is packaged in a 128-pin thin quad flatpack (tqfp). pin configuration (1,2,3)
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperatu re ranges 3 pin configurations (1,2) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. recommended dc operating conditions maximum operating temperature and supply voltage (1) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and the output signals switch from 0v to 3v or from 3v to 0v. capacitance (1) (t a = +25c, f = 1.0mhz) tqfp only notes: 1. this is the parameter t a . this is the "instant on" case temperature. symbol pin name a 0 p1 - a 11 p1 address lines - port 1 a 0 p2 - a 11 p2 address lines - port 2 a 0 p3 - a 11 p3 address lines - port 3 a 0 p4 - a 11 p4 address lines - port 4 i/o 0 p1 - i/o 7 p1 data i/ o - port 1 i/o 0 p2 - i/o 7 p2 data i/ o - port 2 i/o 0 p3 - i/o 7 p3 data i/ o - port 3 i/o 0 p4 - i/o 7 p4 data i/ o - port 4 r/ w p1 read/write - port 1 r/ w p2 read/write - port 2 r/ w p3 read/write - port 3 r/ w p4 read/write - port 4 gnd ground ce p1 chip enab le - port 1 ce p2 chip enab le - port 2 ce p3 chip enab le - port 3 ce p4 chip enab le - port 4 oe p1 output enab le - port 1 oe p2 output enab le - port 2 oe p3 output enab le - port 3 oe p4 output enab le - port 4 v cc power 3241 tbl 01 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gndground 000v v ih input high voltage 2.2 ____ 6.0 (2) v v il input low voltage -0.5 (1 ) ____ 0.8 v 32 41 tbl 02 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 0v 9 pf c out output capacitance v out = 0v 10 pf 3241 tbl 03 grade ambient temperature gnd vcc commercial 0 c to +70 c0v 5.0v + 10% industrial -40c to +85c 0v 5.0v + 10% 3241 tbl 04 symbol rating commercial & industrial unit v term (2) terminal voltage with respect to gnd -0.5 to +7.0 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 3241 tbl 05
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperature ranges 4 notes: 1. 'x' in part number indicates power rating (s or l). 2. v cc = 5v, t a = +25c and are not production tested. 3. f = 0 means no address or control lines change. 4. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 5. for the case of one port, divide the appropriate current above by four. dc electrical characteristics over the operating temperature and supply voltage range (1,5) (v cc = 5.0v 10%) note: 1. at vcc < 2.0v input leakages are undefined. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) symbol parameter test conditions 7054s 7054l unit min. max. min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = 4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2674 tbl 07 symbol parameter condition 7054x20 com'l only 7054x25 com'l & ind 7054x35 com'l only unit version typ. (2) max. typ. (2) max. typ. (2) max. i cc1 operating power supply current (all ports active) ce = v il outputs disabled f = 0 (3) com'l. s l 150 150 300 250 150 150 300 250 150 150 300 250 ma ind. s l ____ ____ ____ ____ 150 150 360 300 150 150 360 300 ma i cc2 dynamic operating current (all ports active) ce = v il outputs disabled f = f max (4) com'l. s l 240 210 370 325 225 195 350 305 210 180 335 290 ma ind. s l ____ ____ ____ ____ 225 195 400 340 210 180 395 330 ma i sb standby current (all ports - ttl level inputs) ce = v ih f = f max (4) com'l. s l 70 60 95 80 60 50 85 70 40 35 75 60 ma ind. s l ____ ____ ____ ____ 60 50 115 85 40 35 110 80 ma i sb1 full standby current (all ports - all cmos level inputs) all ports ce > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) com'l. s l 1.5 0.3 15 1.5 1.5 0.3 15 1.5 1.5 0.3 15 1.5 ma ind. s l ____ ____ ____ ____ 1.5 0.3 30 4.5 1.5 0.3 30 4.5 ma 3241 tbl 06
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperatu re ranges 5 timing waveform of read cycle no. 1, any port (1) note: 1. r/ w = v ih , oe = v il , and ce = v il . ac test conditions figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1 and 2 3241 tbl 08 data out 347 ? 893 ? 30pf 5v 3241 drw 04 data out 347 ? 893 ? 5pf* 5v , 3241 drw 05 t aa t oh t oh data out address t rc data valid previous data valid
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperature ranges 6 timing waveform of read cycle no. 2, any port (1, 2) notes: 1. r/ w = v ih for read cycles. 2. addresses valid prior to or coincident with ce transition low. ac electrical characteristics over the operating temperature and supply voltage (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 3. 'x' in part number indicates power rating (s or l). 7054x20 com'l only 7054x25 com'l & ind 7054x35 com'l only symbol parameter min.max.min.max.min.max.unit read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 10 ____ 15 ____ 25 ns t oh output hold from address change 0 ____ 0 ____ 0 ____ ns t lz output low-z time (1,2) 5 ____ 5 ____ 5 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 15 ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 20 ____ 25 ____ 35 ns 3241 tbl 09 3241 drw 06 t aoe t lz t hz data out ce t ace valid data oe current i cc i sb t pu 50% t lz t pd 50% t hz
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperatu re ranges 7 ac electrical characteristics over the operating temperature and supply voltage (5) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 3. if oe = v il during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp. specified for oe = v ih (refer to ?timing waveform of write cycle?, note 8). 4. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read?. 5. 'x' in part number indicates power rating. 7054x20 com'l only 7054x25 com'l & ind 7054x35 com'l only symbol parameter min. max. min. max. min. max. unit write cycle t wc write cycle time 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ 30 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width (3) 15 ____ 20 ____ 30 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 20 ____ ns t hz output high-z time (1,2) ____ 15 ____ 15 ____ 15 ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 12 ____ 15 ____ 15 ns t ow output active from end-of-write (1,2) 0 ____ 0 ____ 0 ____ ns t wdd write pulse to data delay (4) ____ 35 ____ 45 ____ 55 ns t ddd write data valid to read data delay (4) ____ 30 ____ 35 ____ 45 ns 3241 tbl 10
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperature ranges 8 ce 3241 drw 08 t aw t as t wr t dw data in address t wc r/ w t ew t dh (6) (2) (3) timing waveform of write cycle no. 1, r/ w controlled timing (5,8) timing waveform of write cycle no. 2, ce controlled timing (1,5) notes: 1. r/ w or ce = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w = v ih to the end of write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed but is not production tested. 8. if oe = v il during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . ce 3241 drw 07 t aw t as t wr t dw data in address t wc r/ w t wp data out t wz (7) (4) (4) (2) t ow oe (7) t hz t lz (7) t hz (6) (3) t dh
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperatu re ranges 9 timing waveform of write with port-to-port read (1, 2) functional description the idt7054 provides four ports with separate control, address, and i/o pins that permit independent access for reads or writes to any location in memory. these devices have an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. each port has its own output enable control ( oe ). in the read mode, the port?s oe turns on the output drivers when set low. read/ write conditions are illustrated in the table. table i ? read/write control notes: 1. "h" = v ih , "l" = v il , "x" = don?t care, "z "= high impedance 2. for valid write operation, no more than one port can write to the same address location at the same time. 3241 drw 09 addr "a" t wc data "b" match t wp r/ w "a" data in"a" addr "b" t dh valid match valid t ddd t wdd t dw notes: 1. oe = v il for the reading ports. 2. all timing is the same for left and right ports. port "a" may be either of the four ports and port "b" is any other port. any port (1 ) r/ w ce oe d 0-7 function x h x z port deselected: power-down xhx z ce p1 = ce p2 = ce p3 = ce p4 =v ih power down mode i sb or i sb1 llx data in data on port written into memory (2) hl ldata out data in memory output on port xxh z outputs disabled 3241 tbl 11
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperature ranges 10 ordering information note: 1. industrial temperature range is available. for other speeds, packages and powers contact your sales office. 2. green parts available. for specific speeds, packages and powers contact your local sales office. datasheet document history 1/18/99: initiated datasheet document history converted to new format cosmetic typographical corrections added additional notes to pin configurations 6/4/99: changed drawing format page 1 corrected dsc number 9/1/99: removed preliminary 11/10/99: replaced idt logo 5/23/00: page 4 increased storage temperature parameter clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" changed 200mv to 0mv in notes 10/22/01: page 2 & 3 added date revision for pin configurations page 5, 7 & 8 added industrial temp to column heading for 25ns speed to dc & ac electrical characteristics page 11 added industrial temp offering to 25ns ordering information page 4, 5, 7 & 8 removed industrial temp footnote from all tables page 6 changed 5ns to 3ns in ac test conditions table page 1 & 11 replace tm logo with ? logo
6.42 idt7054s/l high-speed 4k x 8 fourport? static ram industrial and commercial temperatu re ranges 11 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com datasheet document history (con't) 02/20/15: page 1 added green availability to features page 2 removed idt in reference to fabrication page 2 2v battery backup for low-power versions are no longer offered page 2,3 & 10 the package code pk128-1 changed to pk128 to match standard package codes page 10 added tape and reel and green to ordering information pages 1-10 removed all military data including the g108 pin configuration, changed table headings and ordering information to indicate that there is no longer a military offering for this 7054 device

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